Enabling the DRAM and 3D NAND design of today
DRAM has gone through a large number of variations in its architecture since its commercial inception in the 1970s. From PIS planar capacitors to 3D architectures, DRAMs have come a long way in terms of their memory density, and 3D Stack and Trench architecture are currently the main-stay for DRAM memory devices. Such design is made practically feasible only due to the availability of techniques such as ALD which can deposit high quality defect-free ultra-thin single layers and nanolaminates with exceptional uniformity and the ability to conformally coat high aspect ratio structures. The ability to engineer the bandgap of these high-K dielectric materials to ensure low leakage current and good cell capacitance even in the ~5–7nm thickness range makes ALD the go-to technique.
The concept of 3D NAND was introduced in 2007 to overcome the undesirable floating gate challenges in planar NAND as well as to improve the cost of memory bit/unit area. Replacement Gate, which is one of the fundamental aspects of 3D NAND, is not possible without the ALD process. Conformal ALD layers with excellent step coverage over high aspect ratios are required for the high-K gate dielectrics, while an ultra-thin TiN layer is required as a barrier for the W gates.
ALD has been a key enabler for memory devices and will continue to be so in the future.
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